ASIC Design Engineer (Kỹ Sư Thiết Kế Vi Mạch Asic/soc)

ASIC/SoC Design Engineer - Shape the Future of AI Hardware at FPT Telecom!

- Design and implement RTL (Verilog/VHDL) for complex IP blocks, sub-systems, and top-level SoC integration.

- Handle the integration of internal and external IPs into sophisticated SoC architectures.

- Design critical top-level SoC components including IO/PAD-ring, clock and reset distribution, and power management structures.

- Drive the front-end design flow: RTL coding, logic synthesis (including DFT insertion), and rigorous quality checks (Lint, CDC, RDC, Logical Equivalence).

- Develop and verify complex power intent (UPF) for low-power SoCs featuring multiple power and voltage domains.

- Collaborate closely with Chip Architecture, Design Verification, Physical Design, DFT, and Power teams to achieve successful tapeouts on schedule and with the highest quality.

- Contribute to the development and maintenance of design methodologies, flows, and checks.

Why Join FPT?

- Be part of a pioneering team entering the dynamic IC Design market in Vietnam.

- Work on impactful, cutting-edge AI hardware projects.

- Take ownership and contribute significantly to the design of complex SoCs.

- Collaborate with a dynamic and experienced team of experts.

- Grow your career in a leading technology corporation.

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

- Minimum of 3 years of hands-on experience in ASIC/SoC digital design or complex FPGA development.

- Strong proficiency in RTL coding using Verilog and/or VHDL.

- Solid understanding and practical experience with ASIC front-end flows (RTL design, Synthesis, FE Quality Checks).

- Proven expertise in SoC IP integration and sub-system design.

- Experience with standard EDA tools for simulation, synthesis, and FE checks (e.g., Synopsys, Cadence, Mentor).

- Demonstrated experience with FE quality checks: Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and Logical Equivalence Checks (LEC).

- Experience in designing for low power, including developing Power Intent using UPF.

- Excellent analytical and problem-solving skills with a passion for innovation.

- Strong communication and teamwork skills, with the ability to collaborate effectively across multi-disciplinary teams.

Bonus Points:

- Familiarity with Design for Test (DFT) methodologies (Scan, BIST, JTAG).

- Understanding of Static Timing Analysis (STA) concepts and backend-related flows.