ASIC Design Verification Engineer

General Summary

- As a leading technology innovator in Vietnam, FPT is expending and entering new area such as the IC Design market. FPT is looking for bright ASIC engineers with excellent analytical and technical skills. Besides ASIC and/or FPGA design experience, this professional needs to be a great team player with good communication skill. This is a great opportunity to join a fast-paced SoC team responsible for RTL Design, flows and methodology for high performance ASICs which enable AI acceleration in our smart camera design with more efficient TOPs/Watt.

- FPT Telecom is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design/Verification to build IP and System On Chip (SoC) for Edge AI applications.

Our offer

- Development of SoA AI hardware accelerators that redefine efficiency and performance.

- Collaboration with a team of high-level engineers and researchers.

- Work on transformative projects that impact industries worldwide.

Job Description

- The majority of compute effort for Deep Learning inference is based on mathematical operations that can mostly be grouped into four parts: convolutions, activations, pooling, and normalization. These operations share a few characteristics that make them particularly well suited for special-purpose hardware implementation: their memory access patterns are extremely predictable, and they are readily parallelized.

- Many proposed DLA architect exist in the academic literature and also industry such as the NVDLA architecture proposed by NVIDIA Deep Learning Accelerator (DLA) project which promotes a standardized, open architecture to address the computational demands of inference. Or more recently Xilinx proposed AI Engine architecture on its Versal Edge AI series. ARM corporate with NVIDIA in its Trillium project which bring Deep Learning to billions of IoT chip with the Ethos NPU IP.

As an AI Hardware Accelerator Engineer, you'll:

- Design and optimize hardware accelerators tailored for machine learning and AI workloads.

- Implement cutting-edge architectures for high-speed inference computation and low power consumption.

- Collaborate on system-level integration to ensure seamless functionality.

- A degree in electrical engineering, computer engineering, or a related field.

- Knowledge of System-On-Chip or ASIC design, understanding of SoC or ASIC tools/flows.

- Design/Verification skills, System Verilog, UVM.

- RTL Synthesis Coding Solid experience in designing hardware accelerators, including FPGA/ ASIC development.

- Proficiency in hardware description languages (e.g., VHDL, Verilog) and EDA tools.

- Understanding of system level architecture, such as interconnects, memory hierarchy, interrupts, and memory-mapped IO.

- In-depth knowledge of ML/DL Technologies.

- Problem-solving skills and a passion for innovation.