ASIC Layout Designer - Analog/mixed Signal

We are actively seeking skilled ASIC Layout Designer with expertise in analog layout to join our exclusive talent pool for future opportunities in cutting-edge MEMS sensor projects. If you're passionate about ASIC design and have the niche skills we're looking for, we want to hear from you!

While we may not have immediate openings, we recognize that professionals with your expertise are in high demand, and we are eager to stay in touch for future opportunities.

As an ASIC Layout Designer, you will be responsible for:

Analog Layout Design from the block level to top-level IC integration.

Performing physical verification for advanced ASICs in MEMS sensor applications.

Collaborating with international design teams to ensure timely and high-quality layout delivery.

Managing the entire tape-out flow in coordination with the wafer foundry.

Collaborating with digital backend engineers to generate DFE files for P&R and integrating the digital layout into the overall chip.

Working with CAD engineers to continuously enhance our PDKs and design environments.

Bachelor's/Master's in Microelectronics or Electrical Engineering (focus on analog circuits, digital circuits, semiconductor devices, and physics).

Proven experience in analog/mixed-signal IC layout (ADCs, DACs, PLLs, LDOs, charge pumps, bandgap).

Expertise in TSMC 28nm ~ 152nm, SMIC 110nm, and TZ 180nm BCD SOI technologies and design rules.

Proficient in Cadence Virtuoso, verification tools (Calibre, PVS, Assura), and CMOS process effect mitigation.

Familiar with experience in EM/IR drop analysis, Linux OS, and programming (Shell, Skill, Python, Tcl).

Good English communication

Preferred Skills and Experience:

Familiarity with programming languages like Shell, Skill, Python, and Tcl.

Experience leading a full-chip layout from floorplan to tape-out.

Auto place and route experience for non-timing critical designs is a plus.