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Mô Tả Công Việc
• IP/SOC design verification
• Building the RTL design verification team starting from finding well-qualified semiconductor verification engineers
• Review the IP/SOC specification and architecture
• Extract the features and define the verification plan
• Execute on the verification plan through testbench development, test generation, failure analysis, and coverage analysis/closure.
• RTL and gate level simulation
• Design verification methodology and flow implementation and improvement
Yêu Cầu Công Việc
• 6-8 years of experience in related work (SOC design verification)
• Good understanding of computer architecture and Verilog
• Understanding SOC design flow and methodology
• Capability to extract the design features and define the verification plan
• Failure analysis and decision making
• Project schedule management
Preferred Qualifications
• Domain knowledge for CPU, coherent/noncoherent cache system, SOC bus, DRAM controller, accelerators (NPU, GPU, DSP), multimedia and display IP (ISP, video codec, HDMI/DP)
• Working experience of UPF-based power-aware simulation, System Verilog Assertion (SVA), scripts in languages such as Perl and/or Python
• Advanced knowledge of standard SoC design and verification flows including RTL design, simulation and testbench development, coverage analysis and constrained random testing
Preferred Character
• Encouraging team members to be motivated with good coaching skills to accomplish their work
• Good at 1:1 communication with team members knowing what are their personal interests and what are their concerns to build up good relationship
• Facilitating collaboration within and across teams to root-cause and debug issues
• Good decision-making skill respecting team members’ opinions
• Good communication skill to collaborate with HW/SW development teams in HQ