What We Can Offer
Attractive salary + incentive + allowance
Insurance package for family
Training opportunities
Job Description
• Schedules and manages workflow, tasks, design data/documentations
• Normally receives little instruction on day-to-day work, general instructions on new assignments
• Demonstrates good judgment in selecting methods and techniques for obtaining solutions
• Works on custom layout Analog IPs like High-Speed IOs, PLL, DLL, Bandgap, High-Speed macros for PHY, Clock trees
• Floor planning, power design, signal routing strategy, EMIR awareness, parasitic optimization for layout blocks from schematics
• Understands and applies Analog Layout techniques to ensure design meet performance with minimum area and good yield
• Participates in building and enhancing layout flow for faster, higher quality design process
• Does layout verification for DRC/LVS/ERC/ANT/ESD/DFM
• Does PERC verification for ESD/LUP checks
• Completes all design quality checks and data quality checks
• Works with Place and Route engineer to integrate analog layouts into top level
• Does design reviews across global team
• May collaborate in package design (interposer design, RDL design)
• Works closely with design team in Viet Nam, USA and Italy to ensure the success of the whole product
• May join research programs to implement new ideas for future products and flows
• May lead a layout team to complete a full design block
Read full Job Descriptions
• Normally receives little instruction on day-to-day work, general instructions on new assignments
• Demonstrates good judgment in selecting methods and techniques for obtaining solutions
• Works on custom layout Analog IPs like High-Speed IOs, PLL, DLL, Bandgap, High-Speed macros for PHY, Clock trees
• Floor planning, power design, signal routing strategy, EMIR awareness, parasitic optimization for layout blocks from schematics
• Understands and applies Analog Layout techniques to ensure design meet performance with minimum area and good yield
• Participates in building and enhancing layout flow for faster, higher quality design process
• Does layout verification for DRC/LVS/ERC/ANT/ESD/DFM
• Does PERC verification for ESD/LUP checks
• Completes all design quality checks and data quality checks
• Works with Place and Route engineer to integrate analog layouts into top level
• Does design reviews across global team
• May collaborate in package design (interposer design, RDL design)
• Works closely with design team in Viet Nam, USA and Italy to ensure the success of the whole product
• May join research programs to implement new ideas for future products and flows
• May lead a layout team to complete a full design block
Job Requirements
• BS in Electronics Engineering, Telecommunications, Mechatronics or related background.
• From 3 years of experience in custom layout
• Familiar with Layout entry tools, verification tools.
• Understand basic semiconductor fabrication processes
• Understand MOSFET fundamentals
• Understand layout techniques for high speed, matching, ESD, Latchup, Antenna, EMIR
• Experienced with writing layout review presentations and layout verification reports
• Good English communication
• Good team player
• Self-motivated.
• From 3 years of experience in custom layout
• Familiar with Layout entry tools, verification tools.
• Understand basic semiconductor fabrication processes
• Understand MOSFET fundamentals
• Understand layout techniques for high speed, matching, ESD, Latchup, Antenna, EMIR
• Experienced with writing layout review presentations and layout verification reports
• Good English communication
• Good team player
• Self-motivated.
Job Locations
Ho Chi Minh City, Vietnam
