Senior Allegro PCB Layout Design Engineer

Key Responsibilities:

• Design and develop high-quality PCB layouts using Allegro and OrCAD.

• Collaborate with cross-functional teams to define design requirements and specifications.

• Conduct signal integrity (SI) and power integrity (PI) analysis to ensure optimal performance.

• Implement DDR4 design techniques and 50G SERDES standards in PCB layouts.

• Review and validate design documentation for accuracy and compliance.

• Troubleshoot and resolve design issues throughout the development process.

• Mentor junior engineers and provide guidance on best practices in PCB design.

• Proficiency in Allegro and OrCAD for PCB design.

• Strong understanding of signal integrity (SI) and power integrity (PI) principles.

• Experience with DDR4 design and 50G SERDES technologies.

• Excellent problem-solving and analytical skills.

• Effective communication skills in English, both written and verbal.

• Ability to work collaboratively in a team-oriented environment.

• Detail-oriented with a strong focus on quality and accuracy.

• Minimum of seven years of experience in PCB layout design using Allegro and OrCAD.

• Proven experience in signal integrity (SI) and power integrity (PI) analysis.

• Hands-on experience with DDR4 design and 50G SERDES.

• Experienced with EMC/EMI mitigation techniques and thermal analysis.

• A background in telecom or cybersecurity industries is preferred.