Các Phúc Lợi Dành Cho Bạn
Competitive salary and bonus
Professional and active working environment
Social insurance, health insurance, unemployment insurance according to Labor Laws
Mô Tả Công Việc
As a member of the central physical design team, you will provide backend design service for multiple Marvell SOC design groups, from floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity analysis, to physical verification (DRC/LVS/Antenna). You will have the opportunity to work on many varieties of challenging designs, i.e. low power and high-speed SOCs. You will work closely with the frontend and integration team to ensure successful tapeouts.
Xem toàn bộ Mô Tả Công Việc
Yêu Cầu Công Việc
•BS/MS in EE/CS with 3+ years of hands-on experience in frontend design integration (synthesis/timing), backend place and route or layout integration.
•Familiar with physical design methodologies and deep sub-micron technology issues. Familiar with ASIC design flow, Verilog HDL, chip synthesis and timing closure.
•Must be programming-minded, write makefile/Tcl/Perl to automate design process and improve efficiency.
•Detail oriented, self-motivated team worker, good verbal and written communication skills.
•Good understanding of Synopsys suite (Astro, Apollo, JupiterXT, Physical Compiler, IC Compiler), Magma suite (Talus/Blast), or Cadence suite (EDI, SOC Encounter, Nanoroute).
•Knowledge on static timing analysis (PrimeTime), EM/IR-Drop/Xtalk analysis (Celtic, PT-SI, Apache, AstroRail, PrimeRail), formal or physical verification (Formality, Verplex/LEC, Calibre, Hercules) a plus.
Địa Điểm Làm Việc
Ho Chi Minh City, Vietnam