STA Engineer

As an ASIC STA engineer, you will be responsible for all aspects of timing including, working with designers for timing changes, helping construct/modify flows, timing analysis and timing closure.

Responsibilities

-Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation).

-Develop and maintain methodology and flows related to timing verification and closure.

-Generation of block and full chip timing constraints.

-Analyze timing reports and utilize scripting techniques to develop insights and drive rapid timing closure.

-Work with the physical design team to close and sign-off on timing.

-Bachelor's or Master's degree in Electrical Engineering or Electronic Engineering.

-At least 2+ years hands-on experience in ASIC timing constraints generation and timing closure.

-Expertise in STA tools (such as Primetime) and methodologies for timing closure with a good understanding of OCV, noise and cross-talk effects on timing.

-Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced process technology nodes (28nm and below).

-Knowledge of timing corners/modes and process variations.

-Knowledge of low-power techniques including clock gating, power gating and multi-voltage designs.

-Proficient in scripting languages (Tcl and Perl).

-Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups (e.g. digital design, verification, DFT, physical design, etc.).

-Familiarity with RTL, synthesis, logic equivalence, DFT, floor-planning, and backend related methodology and tools.

Nice to have:

-Good knowledge in digital design techniques and the state-of-the-art physical design methods.

-Solid fundamentals in IC design flow and ASIC concepts.